1. Field of the Invention
This present invention relates to a semiconductor memory and a method for manufacturing a semiconductor memory.
2. Description of the Related Art
An electrically erasable programmable read-only memory (EEPROM) is known as a non-volatile semiconductor memory. In the EEPROM, a cell array is configured in such a way that a memory cell transistor is arranged at an intersection where a word line in the row direction and a bit line in the column direction cross over each other. Among the various EEPROMs, the NAND flash EEPROM in which a plurality of memory cell transistors are connected in series, and which can erase all the written data simultaneously, has been in wide use.
Each of the memory cell transistors of the non-volatile semiconductor memory has an insulated gate structure, and forms a stacked gate structure in which a floating gate electrode and a control gate electrode are stacked on a channel region. Between the control gate electrode and the floating gate electrode, an inter-electrode insulating film (interpoly) is disposed, and a gate insulating film (tunnel oxide film) is disposed between the channel region and the floating gate electrode. The floating gate electrodes adjacent to each other and the control gate electrodes adjacent to each other individually have the same structures.
The control gate electrode drives the floating gate electrode which electrically floats. In order to efficiently apply, to the floating gate electrode, a bias applied to the control gate electrode, it is necessary to increase the capacitance of a portion of the inter-electrode insulating film between the floating gate electrode and the control gate electrode. The increased capacitance should be greater than a capacitance of a portion of the gate insulating film between the floating gate electrode and the channel region when the inter-electrode insulating film and the gate insulating film are of the same thickness and material. For this purpose, a method is known which provides the inter-electrode insulating film and the control gate electrode from an upper surface of the floating gate electrode to a floating gate electrode adjacent thereto. This method increases the area where the upper and side surfaces of the floating gate electrode and the control gate electrode are opposite to each other. This increased area is larger than an area where only a lower surface of the floating gate electrode and the channel region are opposite to each other. By this method, the capacitance between the floating gate electrode and the control gate electrode is increased more than the capacitance between the floating gate electrode and the channel region.
However, as the memory cell transistor has continued to be integrated/miniaturized, the distance between the adjacent gate electrodes has become more narrow. Therefore, it has become difficult to arrange the inter-electrode insulating film and the control gate electrode between the adjacent floating gate electrodes. Hence, it has become difficult to increase the capacitance between the floating gate electrode and the control gate electrode more than the capacitance between the floating gate electrode and the channel region.
Moreover, since the distance between gates adjacent to each other has become narrow, the capacitance between the adjacent gates is increased. Owing to an influence from the capacitance between the adjacent gates, a threshold value of the memory cell transistor in which writing operation is not performed is varied, sometimes resulting in deterioration of write accuracy.